Phase Locked Loop 2.0

surya deopa
273
1
0
0
Frequency Detection and FPGA slot
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Phase Locked Loop
Phase Locked Loop

surya deopa

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Public Domain /

Published: October 8, 2018 In development

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Design Files

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Component (14)
Qty
Description
SN74HC4040N

U2

1
12-Bit Asynchronous Binary Counter
Capacitor

C2

1
Generic Capacitor (Non-Polarized) (.33u)
CD74HC297

U3

1
No description
4 input jumper

U26

1
No description

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Export Design Data

Open JSON Format
All model data in Upverter's Open JSON export format (more info)
Gerber Format (RS-274X extended)
CAD to CAM transfer instructions (more info)
NC Drill (Excellon)
NC drill and route machine instructions (more info)
XYRS
X-Y, rotation and side data for Pick and Place assembly (CSV)
PADS Layout Netlist
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Dimension Drawing
Export the board outline, holes, and rulers
High-Res Schematic PNG
High resolution image form
3D Model (Step)
3D model of the board and components

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