Analog Devices AD9880

Reference Designs (1)

Attributes

Part Number
Manufacturer
Datasheet
Prefix
U
Digikey Description
Digikey Part Number
Lead Free
Yes
Mouser Part Number
Octopart Part Number
Package
LQFP100
RoHS
Yes
Temperature Range High
Temperature Range Low

Pins

1
GND
2
GREEN 7
3
GREEN 6
4
GREEN 5
5
GREEN 4
6
GREEN 3
7
GREEN 3
8
GREEN 1
9
GREEN 0
10
VDD
11
GND
12
BLUE 7
13
BLUE 6
14
BLUE 5
15
BLUE 4
16
BLUE 3
17
BLUE 2
18
BLUE 1
19
BLUE 0
20
MCLKIN
21
MCLKOUT
22
SCLK
23
LRCLK
24
I2S3
25
I2S2
26
I2S1
27
I2S0
28
S/PDIF
29
GND
30
DV_DD
31
GND
32
DVDD
33
VD
34
RX0-
35
RX0+
36
GND
37
RX1-
38
RX1+
39
GND
40
RX2-
41
RX2+
42
GND
43
RXC+
44
RXC-
45
VD
46
RTERM
47
GND
48
DVDD
49
DDC_SCL
50
DDC_SDA
51
MCL
52
MDA
53
ALGND
54
PVDD
55
GND
56
PVDD
57
FILT
58
GND
59
PVDD
60
VSYNC 1
61
VSYNC 0
62
EXTCLK/COAST
63
HSYNC 1
64
HSYNC 0
65
GND
66
BAIN1
67
VD
68
BAIN0
69
GND
70
SOGIN1
71
GAIN1
72
VD
73
SOGIN0
74
GAIN0
75
GND
76
VD
77
RAIN1
78
GND
79
RAIN0
80
VD
81
PWRDN
82
SCL
83
SDA
84
O/E FIELD
85
VSOUT
86
SOGOUT
87
HSOUT
88
DE
89
DATACLK
90
VDD
91
GND
92
RED 7
93
RED 6
94
RED 5
95
RED 4
96
RED 3
97
RED 2
98
RED 1
99
RED 0
100
VDD

Contributors

Datasheet Preview

Analog/HDMI
Dual Display Interface
AD9880
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Analog/HDMI dual interface
Supports high bandwidth digital content protection
RGB-to-YCbCr 2-way color conversion
Automated clamping level adjustment
1.8 V/3.3 V power supply
100-lead LQFP Pb-free package
RGB and YCbCr output formats
Analog interface
8-bit triple ADC
100 MSPS maximum conversion rate
Macrovision® detection
2:1 input mux
Full sync processing
Sync detect for hot plugging
Midscale clamping
Digital video interface
HDMI v 1.1, DVI v 1.0
150 MHz HDMI receiver
Supports high bandwidth digital content protection
(HDCP 1.1)
Digital audio interface
HDMI 1.1-compatible audio interface
S/PDIF (IEC90658-compatible) digital audio output
Multichannel I2S audio output (up to 8 channels)
APPLICATIONS
Advanced TV
HDTV
Projectors
LCD monitor
GENERAL DESCRIPTION
The AD9880 offers designers the flexibility of an analog interface
and high definition multimedia interface (HDMI) receiver inte-
grated on a single chip. Also included is support for high band-
width digital content protection (HDCP).
Analog Interface
The AD9880 is a complete 8-bit 150 MSPS monolithic analog inter-
face optimized for capturing component video (YPbPr) and RGB
graphics signals. Its 150 MSPS encode rate capability and full power
analog bandwidth of 330 MHz supports all HDTV formats (up to
1080 p) and FPD resolutions up to SXGA (1280 × 1024 @ 75 Hz).
The analog interface includes a 150 MHz triple ADC with internal
1.25 V reference, a phase-locked loop (PLL), and programmable
gain, offset, and clamp control. The user provides only 1.8 V and
3.3 V power supplies, analog input, and Hsync. Three-state
FUNCTIONAL BLOCK DIAGRAM
DATACK
DE
V
SYNC
SYNC
PROCESSING
AND
CLOCK
GENERATION
DATACK
2
REF
HSOUT
VSOUT
SOGOUT
HDMI RECEIVER
DIGITAL INTERFACE
REFOUT
REFIN
CLAMP
A/D
2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX
SPDIF OUT
8-CHANNEL
I
2
SOUT
2
MCLK
LRCLK
HDCP
2
DATACK
HSOUT
VSOUT
SOGOUT
DE
MUXES
RGB YCbCr MATRIX
R/G/B 8X3
OR YCbCr
R/G/B 8X3
or YCbCr
YCbCr (4:2:2
OR 4:4:4)
AD9880
R/G/B OR YPbPr
IN0
R/G/B OR YPbPr
IN1
HSYNC 0
HSYNC 1
HSYNC 0
HSYNC 1
SOGIN 0
SOGIN 1
COAST
CKINV
CKEXT
FILT
SCL
SDA
RX1+
RX1–
RX2+
RX2–
RXC+
RXC–
R
TERM
MCL
MDA
DDCSCL
DDCSDA
RX0+
RX0–
H
SYNC
R/G/B 8X3
SERIAL REGISTER
AND
POWER MANAGEMENT
ANALOG INTERFACE
05087-001
SCLK
4
Figure 1.
CMOS outputs can be powered from 1.8 V to 3.3 V. The
AD9880’s on-chip PLL generates a pixel clock from Hsync. Pixel
clock output frequencies range from 12 MHz to 150 MHz. PLL
clock jitter is typically less than 700 ps p-p at 150 MHz. The
AD9880 also offers full sync processing for composite sync and
sync-on-green (SOG) applications.
Digital Interface
The AD9880 contains a HDMI 1.1-compatible receiver and sup-
ports all HDTV formats (up to 1080 p and 720 p) and display
resolutions up to SXGA (1280 × 1024 @75 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays can now receive encrypted
video content. The AD9880 allows for authentication of a video
receiver, decryption of encoded data at the receiver, and renewa-
bility of the authentication during transmission, as specified by the
HDCP v 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9880 is provided
in a space-saving, 100-lead LQFP surface-mount Pb-free plastic
package and is specified over the 0°C to 70°C temperature range.
AD9880
Rev. 0 | Page 2 of 64
TABLE OF CONTENTS
Specifications..................................................................................... 3
Analog Interface Electrical Characteristics............................... 3
Digital Interface Electrical Characteristics ............................... 4
Absolute Maximum Ratings............................................................ 6
Explanation of Test Levels........................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Design Guide................................................................................... 12
General Description................................................................... 12
Digital Inputs .............................................................................. 12
Analog Input Signal Handling.................................................. 12
Hsync and Vsync Inputs............................................................ 12
Serial Control Port ..................................................................... 12
Output Signal Handling............................................................. 12
Clamping ..................................................................................... 12
Timing.......................................................................................... 16
HDMI Receiver........................................................................... 20
DE Generator .............................................................................. 20
4:4:4 to 4:2:2 Filter ...................................................................... 20
Audio PLL Setup......................................................................... 21
Audio Board Level Muting........................................................ 21
Timing Diagrams ....................................................................... 21
2-Wire Serial Register Map ........................................................... 23
2-Wire Serial Control Register Detail.......................................... 37
Chip Identification ..................................................................... 37
PLL Divider Control .................................................................. 37
Clock Generator Control .......................................................... 37
Input Gain ................................................................................... 38
Input Offset ................................................................................. 38
Sync .............................................................................................. 39
Coast and Clamp Controls........................................................ 39
Status of Detected Signals ......................................................... 40
Polarity Status ............................................................................. 41
BT656 Generation...................................................................... 46
Macrovision................................................................................. 48
Color Space Conversion ............................................................ 49
2-Wire Serial Control Port........................................................ 56
PCB Layout Recommendations.................................................... 58
Color Space Converter (CSC) Common Settings...................... 60
Outline Dimensions ....................................................................... 62
Ordering Guide .......................................................................... 62
REVISION HISTORY
8/05—Revision 0: Initial Version
AD9880
Rev. 0 | Page 3 of 64
SPECIFICATIONS
ANALOG INTERFACE ELECTRICAL CHARACTERISTICS
V
DD,
V
D
= 3.3 V, DV
DD
= PV
DD
= 1.8 V, ADC clock = maximum.
Table 1.
AD9880KSTZ-100 AD9880KSTZ-150
Parameter Temp Test Level Min Typ Max Min Typ Max Unit
RESOLUTION 8 8 Bits
DC ACCURACY
Differential Nonlinearity 25°C I –0.6
+1.6/–
1.0
±0.7
+1.8/–
1.0
LSB
Integral Nonlinearity 25°C I ±1.0 ±2.1 ±1.1 ±2.25 LSB
No Missing Codes Full Guaranteed Guaranteed
ANALOG INPUT
Input Voltage Range
Minimum Full VI 0.5 0.5 V p–p
Maximum Full VI 1.0 1.0 V p–p
Gain Tempco +25°C V 100 220 ppm/°C
Input Bias Current +25°C V 0.2 1 μA
Input Full-Scale Matching
25C
Full
VI
VI
1.25
1.50
5
7
1.25
1.50
5
7
%FS
%FS
Offset Adjustment Range Full V 50 50 %FS
SWITCHING PERFORMANCE
1
Maximum Conversion Rate Full VI 100 150 MSPS
Minimum Conversion Rate Full VI 10 10 MSPS
Data to Clock Skew Full IV −0.5 +2.0 −0.5 +2.0 ns
Serial Port Timing
t
BUFF
Full VI 4.7 4.7 μs
t
STAH
Full VI 4.0 4.0 μs
t
DHO
Full VI 0 0 μs
t
DAL
Full VI 4.7 4.7 μs
t
DAH
Full VI 4.0 4.0 μs
t
DSU
Full VI 250 250 ns
t
STASU
Full VI 4.7 4.7 μs
t
STOSU
Full VI 4.0 4.0 μs
HSYNC Input Frequency Full VI 15 110 15 110 KHz
Maximum PLL Clock Rate Full VI 100 150 MHz
Minimum PLL Clock Rate Full IV 12 12 MHz
PLL Jitter +25°C IV 700 700 ps p-p
Sampling Phase Tempco Full IV 15 15 ps/°C
DIGITAL INPUTS: (5V tolerant)
Input Voltage, High (V
IH
) Full VI 2.6 2.6 V
Input Voltage, Low (V
IL
) Full VI 0.8 0.8 V
Input Current, High (I
IH
) Full V -82 -82 μA
Input Current, Low (I
IL
) Full V 82 82 μA
Input Capacitance 25°C V 3 3 pF
DIGITAL OUTPUTS
Output Voltage, High (V
OH
) Full VI V
DD
− 0.1 V
DD
− 0.1 V
Output Voltage, Low (V
OL
) Full VI 0.4 0.4 V
Duty Cycle, DATACK Full V 45 50 55 45 50 55 %
Output Coding Binary Binary
POWER SUPPLY
V
D
Supply Voltage Full IV 3.15 3.3 3.47 3.15 3.3 3.47 V
DV
DD
Supply Voltage Full IV 1.7 1.8 1.9 1.7 1.8 1.9 V
AD9880
Rev. 0 | Page 4 of 64
AD9880KSTZ-100 AD9880KSTZ-150
Parameter Temp Test Level Min Typ Max Min Typ Max Unit
V
DD
Supply Voltage Full IV 1.7 3.3 3.47 1.7 3.3 3.47 V
PV
DD
Supply Voltage Full IV 1.7 1.8 1.9 1.7 1.8 1.9 V
I
D
Supply Current (V
D
) 25°C VI 260 300 330 mA
I
DVDD
Supply Current (DV
DD
) 25°C VI 45 60 85
I
DD
Supply Current (V
DD
)
2
25°C VI 37 100
3
130
3
mA
IP
VDD
Supply Current (P
VDD
) 25°C VI 10 15 20 mA
Total Power Full VI 1.1 1.4 1.15 1.4 W
Power-Down Dissipation Full VI 130 130 mW
DYNAMIC PERFORMANCE
Analog Bandwidth, Full
Power
25°C V 330 330 MHz
Signal–to–Noise Ratio (SNR) 25°C I 46 46 dB
Without Harmonics Full V 45 45 dB
f
IN
= 40.7 MHz
Crosstalk Full V 60 60 dBc
THERMAL CHARACTERISTICS
θ
JA
-Junction-to-Ambient V 35 35 °C/W
1
Drive strength = high.
2
DATACK load = 15 pF, data load = 5 pF.
3
Specified current and power values with a worst case pattern (on/off).
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS
V
DD
= V
D
=3.3 V, DV
DD
= PV
DD
= 1.8 V, ADC clock = maximum.
Table 2.
AD9880KSTZ-100
AD9880KSTZ-150
Parameter
Tes t
Level
Conditions Min Typ Max Min Typ Max Unit
RESOLUTION 8 8 Bit
DC DIGITAL I/O Specifications
High-Level Input Voltage, (V
IH
) VI 2.5 2.5 V
Low-Level Input Voltage, (V
IL
) VI 0.8 0.8 V
High-Level Output Voltage, (V
OH
) VI V
DD
− 0.1 V
Low-Level Output Voltage, (V
OL
) VI V
DD
− 0.1 0.1 0.1 V
DC SPECIFICATIONS
Output High Level IV Output drive = high 36 36 mA
(I
OHD
) (V
OUT
= V
OH
) IV Output drive = low 24 24 mA
Output Low Level IV Output drive = high 12 12 mA
I
OLD
, (V
OUT
= V
OL
) IV Output drive = low 8 8 mA
DATACK High Level IV Output drive = high 40 40 mA
V
OHC
, (V
OUT
= V
OH
) IV Output drive = low 20 20 mA
DATACK Low Level IV Output drive = high 30 30 mA
V
OLC
, (V
OUT
= V
OL
) IV Output drive = low 15 15 mA
Differential Input Voltage, Single Ended
Amplitude
IV 75 700 75 700 mV