Generic 74HC164

Reference Designs (2)

Attributes

Part Number
Manufacturer
Datasheet
Prefix
U
Digikey Description
Digikey Part Number
Imported From Octopart
yes
Lead Free
Yes
Mouser Part Number
Octopart Part Number
61d5a8df17cfbe12
Package
DIP-14
RoHS
Yes
Temperature Range High
Temperature Range Low
Frequency
62 MHz
Lifecycle Status
Active
Max Supply Voltage Dc
6 V
Min Supply Voltage Dc
2 V
Mounting Type
through hole
Number Of Circuits
8
Output Current Drive
-1 mA
Voltage Nodes
2 V

Pins

1
A
2
B
3
Qa
4
Qb
5
Qc
6
Qd
7
Gnd
8
Clk
9
Clr
10
Qe
11
Qf
12
Qg
13
Qh
14
Vcc

Pricing

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Supplier Part Number # In Stock 1102550100200  
Arrow (USD) SN74HC164N 5148 0.30580.1965 Buy Now
Digi-Key (USD) 296-8248-5-ND 2695 0.420.360.2688 Buy Now
Newark (USD) 69K3680 741 0.4220.3540.215 Buy Now
Verical (USD) SN74HC164N 5125 0.1371 Buy Now
Rochester Electronics (USD) SN74HC164N 111075 0.150.140.14 Buy Now
Mouser (USD) 595-SN74HC164N 5394 0.410.3470.211 Buy Now
Avnet (USD) SN74HC164N 8151 0.46060.26850.20040.1845 Buy Now
Chip One Stop (JPY) TI01-0129135 3350 42.329.426.4 Buy Now
Farnell (GBP) 1287514 2181 0.5460.3690.3180.3050.166 Buy Now
element14 APAC (SGD) 1287514 1707 0.6570.5630.421 Buy Now

Contributors

Datasheet Preview

 
    
SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max I
CC
D Typical t
pd
= 20 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D AND-Gated (Enable/Disable) Serial Inputs
D Fully Buffered Clock and Serial Inputs
D Direct Clear
description/ordering information
These 8-bit shift registers feature AND-gated
serial inputs and an asynchronous clear (CLR
)
input. The gated serial (A and B) inputs permit
complete control over incoming data; a low at
either input inhibits entry of the new data and
resets the first flip-flop to the low level at the next
clock (CLK) pulse. A high-level input enables the
other input, which then determines the state of the
first flip-flop. Data at the serial inputs can be
changed while CLK is high or low, provided the
minimum setup time requirements are met.
Clocking occurs on the low-to-high-level transition
of CLK.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N Tube of 25 SN74HC164N SN74HC164N
Tube of 50 SN74HC164D
SOIC − D
Reel of 2500 SN74HC164DR
HC164
−40°C to 85°C
SOIC − D
Reel of 250 SN74HC164DT
HC164
−40°C to 85°C
SOP − NS Reel of 2000 SN74HC164NSR HC164
Tube of 90 SN74HC164PW
TSSOP − PW
Reel of 2000 SN74HC164PWR
HC164
TSSOP − PW
Reel of 250 SN74HC164PWT
HC164
CDIP − J Tube of 25 SNJ54HC164J SNJ54HC164J
−55°C to 125°C
CFP − W Tube of 150 SNJ54HC164W SNJ54HC164W
−55 C to 125 C
LCCC − FK Tube of 55 SNJ54HC164FK SNJ54HC164FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54HC164 ...J OR W PACKAGE
SN74HC164 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
A
B
Q
A
Q
B
Q
C
Q
D
GND
V
CC
Q
H
Q
G
Q
F
Q
E
CLR
CLK
3212019
910111213
4
5
6
7
8
18
17
16
15
14
Q
G
NC
Q
F
NC
Q
E
Q
A
NC
Q
B
NC
Q
C
B
A
NC
CLK
CLR
V
Q
D
GND
NC
SN54HC164 . . . FK PACKAGE
(TOP VIEW)
CC
H
Q
NC − No internal connection
Copyright 2003, Texas Instruments Incorporated
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SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS OUTPUTS
CLR CLK A B Q
A
Q
B
...Q
H
L X X X L L L
H LXXQ
A0
Q
B0
Q
H0
H HHHQ
An
Q
Gn
H LXLQ
An
Q
Gn
H X L L Q
An
Q
Gn
Q
A0
, Q
B0
, Q
H0
= the level of Q
A
, Q
B
, or Q
H
, respectively,
before the indicated steady-state input conditions were
established
Q
An
, Q
Gn
= the level of Q
A
or Q
G
before the most recent
transition of CLK: indicates a 1-bit shift
logic diagram (positive logic)
9
A
B
CLR
CLK
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
C1
1D
R
3
Q
A
C1
1D
R
4
Q
B
C1
1D
R
5
Q
C
C1
1D
R
6
Q
D
C1
1D
R
10
Q
E
C1
1D
R
11
Q
F
C1
1D
R
12
Q
G
C1
1D
R
13
Q
H
2
1
8
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    
SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
typical clear, shift, and clear sequence
CLK
A
B
CLR
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Clear Clear
Serial InputsOutputs
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
−0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
 
    
SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HC164 SN74HC164
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 2 5 6 2 5 6 V
V
CC
= 2 V 1.5 1.5
V
IH
High-level input voltage
V
CC
= 4.5 V
3.15 3.15
V
V
IH
High-level input voltage
V
CC
= 6 V 4.2 4.2
V
V
CC
= 2 V 0.5 0.5
V
IL
Low-level input voltage
V
CC
= 4.5 V
1.35 1.35
V
V
IL
Low-level input voltage
V
CC
= 6 V 1.8 1.8
V
V
I
Input voltage 0 V
CC
0 V
CC
V
V
O
Output voltage 0 V
CC
0 V
CC
V
V
CC
= 2 V 1000 1000
t/v
Input transition rise/fall time
V
CC
= 4.5 V
500 500
ns
t/v
Input transition rise/fall time
V
CC
= 6 V 400 400
ns
T
A
Operating free-air temperature −55 125 −40 85 °C
NOTE 3: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
If this device is used in the threshold region (from V
IL
max = 0.5 V to V
IH
min = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at t
t
= 1000 ns and V
CC
= 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
T
A
= 25°C SN54HC164 SN74HC164
UNIT
PARAMETER
TEST CONDITIONS
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
I
OH
= −20 µA
4.5 V 4.4 4.499 4.4 4.4
V
OH
V
I
= V
IH
or V
IL
I
OH
= −20 µA
6 V 5.9 5.999 5.9 5.9
V
V
OH
V
I
= V
IH
or V
IL
I
OH
= −4 mA 4.5 V 3.98 4.3 3.7 3.84
V
I
OH
= −5.2 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
I
OL
= 20 µA
4.5 V 0.001 0.1 0.1 0.1
V
OL
V
I
= V
IH
or V
IL
I
OL
= 20 µA
6 V 0.001 0.1 0.1 0.1
V
V
OL
V
I
= V
IH
or V
IL
I
OL
= 4 mA 4.5 V 0.17 0.26 0.4 0.33
V
I
OL
= 5.2 mA 6 V 0.15 0.26 0.4 0.33
I
I
V
I
= V
CC
or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
I
CC
V
I
= V
CC
or 0, I
O
= 0 6 V 8 160 80 µA
C
i
2 V to 6 V 3 10 10 10 pF