Atmel ATTINY85V-10SU

Reference Designs (8)

Attributes

Part Number
Manufacturer
Description
Datasheet
Prefix
U
Digikey Description
Digikey Part Number
Lead Free
Unknown
Mouser Part Number
Octopart Part Number
469e8f932a6e9959
Package
SOIC
RoHS
Unknown
Temperature Range High
Temperature Range Low
Eeprom
512 bytes
Flash Memory
8K
Internal Sram
512 bytes
Maximum Clock Frequency
10MHz
Programmable I/o Lines
6

Pins

1
(PCINT5/RESET'/ADC0/dW) PB5
2
(PCINT3/XTAL1/CLKI/OC1B'/ADC3) PB3
3
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
4
GND
5
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A'/AREF/PCINT0)
6
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
7
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
8
VCC

Contributors

Datasheet Preview

Features
High Performance, Low Power AVR
®
8-Bit Microcontroller
Advanced RISC Architecture
120 Powerful Instructions – Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Non-volatile Program and Data Memories
2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny25/45/85)
Endurance: 10,000 Write/Erase Cycles
128/256/512 Bytes In-System Programmable EEPROM (ATtiny25/45/85)
Endurance: 100,000 Write/Erase Cycles
128/256/512 Bytes Internal SRAM (ATtiny25/45/85)
Programming Lock for Self-Programming Flash Program and EEPROM Data
Security
Peripheral Features
8-bit Timer/Counter with Prescaler and Two PWM Channels
8-bit High Speed Timer/Counter with Separate Prescaler
2 High Frequency PWM Outputs with Separate Output Compare Registers
Programmable Dead Time Generator
USI – Universal Serial Interface with Start Condition Detector
10-bit ADC
4 Single Ended Channels
2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
Temperature Measurement
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Special Microcontroller Features
debugWIRE On-chip Debug System
In-System Programmable via SPI Port
External and Internal Interrupt Sources
Low Power Idle, ADC Noise Reduction, and Power-down Modes
Enhanced Power-on Reset Circuit
Programmable Brown-out Detection Circuit
Internal Calibrated Oscillator
I/O and Packages
Six Programmable I/O Lines
8-pin PDIP, 8-pin SOIC and 20-pad QFN/MLF
Operating Voltage
1.8 - 5.5V for ATtiny25/45/85V
2.7 - 5.5V for ATtiny25/45/85
Speed Grade
ATtiny25/45/85V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
ATtiny25/45/85: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
Industrial Temperature Range
Low Power Consumption
Active Mode:
1 MHz, 1.8V: 300 μA
Power-down Mode:
0.1μA at 1.8V
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
ATtiny25/V*
ATtiny45/V
ATtiny85/V*
*Preliminary
2586J–AVR–12/06
2
2586J–AVR–12/06
ATtiny25/45/85
1. Pin Configurations
Figure 1-1. Pinout ATtiny25/45/85
1
2
3
4
8
7
6
5
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
GND
VCC
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
PDIP/SOIC
1
2
3
4
5
QFN/MLF
15
14
13
12
11
20
19
18
17
16
6
7
8
9
10
DNC
DNC
GND
DNC
DNC
DNC
DNC
DNC
DNC
DNC
NOTE: Bottom pad should be soldered to ground.
DNC: Do Not Connect
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
DNC
DNC
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
VCC
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
DNC
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
3
2586J–AVR–12/06
ATtiny25/45/85
2. Overview
The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
PROGRAM
COUNTER
INTERNAL
OSCILLA
TOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTER0
SERIAL
UNIVERSAL
INTERFACE
TIMER/
COUNTER1
INSTRUCTION
DECODER
DATA DIR.
REG.PORT B
DATA REGISTER
PORT B
PROGRAMMING
LOGIC
TIMING AND
CONTROL
MCU STATUS
REGISTER
STATUS
REGISTER
ALU
PORT B DRIVERS
PB0-PB5
VCC
GND
CONTROL
LINES
8-BIT DATABUS
Z
ADC /
ANALOG COMPARATOR
INTERRUPT
UNIT
DATA
EEPROM
CALIBRATED
OSCILLATORS
Y
X
RESET
4
2586J–AVR–12/06
ATtiny25/45/85
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATtiny25/45/85 provides the following features: 2/4/8K byte of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32
general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high
speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel,
10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software select-
able power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The
Power-down mode saves the register contents, disabling all chip functions until the next Inter-
rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.
2.2 Pin Descriptions
2.2.1 VCC
Supply voltage.
2.2.2 GND
Ground.
2.2.3 Port B (PB5..PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny25/45/85 as listed on
page 61.
On the ATtiny25 device the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged
in the ATtiny15 compatibility mode for supporting the backward compatibility with ATtiny15.
2.2.4 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 23-3 on page
170. Shorter pulses are not guaranteed to generate a reset.