Texas Instruments TPS55330RTE

Reference Designs (5)

Attributes

Part Number
Manufacturer
Datasheet
Prefix
U
Category
DC - DC Converters
Category
Power Management
Category
Semiconductors and Actives
Digikey Description
Digikey Part Number
Imported From Octopart
yes
Lead Free
yes
Mouser Part Number
Octopart Part Number
f8e63053f81a2721
Package
WQFN (RTE)
RoHS
yes
Temperature Range High
Temperature Range Low
Lifecycle Status
Active
Number Of Outputs
1
Number Of Regulated Outputs
1
Output Current
5 A
Quiescent Current
500 uA
Topology
Boost

Pins

1
SW
2
VIN
3
EN
4
SS
5
SYNC
6
AGND
7
COMP
8
FB
9
FREQ
10
NC
11
PGND
12
PGND
13
PGND
14
NC
15
SW
16
SW
17
PowerPAD

Pricing

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Supplier Part Number # In Stock 1310202550  
Arrow (USD) TPS55330RTET**MULT1 3 4.1833.7113.569 Buy Now
Digi-Key (USD) 296-36219-1-ND 2715 4.944.432 Buy Now
Digi-Key (USD) 296-36219-6-ND 2715 4.944.432 Buy Now
Digi-Key (USD) 296-36219-2-ND 2250 Buy Now
Newark (USD) 06X1033 265 5.024.514.213.98 Buy Now
Verical (USD) TPS55330RTET 3 4.183 Buy Now
Mouser (USD) 595-TPS55330RTET 1683 4.794.34.01 Buy Now
Avnet (USD) TPS55330RTET 0 Buy Now
Chip One Stop (JPY) TI01-0326468 241 485.0414.0330.0 Buy Now
Chip One Stop (JPY) TI01-0336066 3 578.0 Buy Now
Avnet Asia (USD) TPS55330RTET 0 Buy Now
Farnell (GBP) 2347002 265 3.712.982.63 Buy Now
Farnell (GBP) 2437646 0 Buy Now
element14 APAC (SGD) 2347002 265 7.736.93 Buy Now
Avnet Europe (EUR) TPS55330RTET 250 Buy Now

Contributors

Datasheet Preview

50
55
60
65
70
75
80
85
90
95
100
0 0.5 1 1.5 2 2.5 3
Output Current (A)
Efficiency (%)
V
IN
= 2.9 V
V
IN
= 3.6 V
V
IN
= 4.2 V
f
SW
= 600 kHz
V
OUT
= 5 V
G017
TPS55330
VIN
EN
SW
SW
SW
FREQ
SS
COMP
SYNC
FB
PGND
PGND
PGND
V
IN
V
OUT
R
SL
R
SH
L
D
C
I
C
O
R
FREQ
C
SS
R
C
C
C
AGND
TPS55330
www.ti.com
SLVSBX8 MAY 2013
Integrated 5-A 24-V Boost/SEPIC/Flyback DC-DC Regulator
Check for Samples: TPS55330
1
FEATURES
DESCRIPTION
The TPS55330 is a monolithic non-synchronous
2
Internal 5-A, 24-V Low-Side MOSFET Switch
switching regulator with integrated 5-A, 24-V power
2.9-V to 16-V Input Voltage Range
switch. It can be configured in several standard
±0.7% Reference Voltage
switching-regulator topologies, including boost,
SEPIC and isolated flyback. The device has a wide
0.5mA Operating Quiescent Current
input voltage range to support applications with input
2.7µA Shutdown Supply Current
voltage from multi-cell batteries or regulated 3.3-V,
Fixed Frequency Current Mode PWM Control
5-V, and 12-V power rails.
Frequency Adjustable from 100kHz to 1.2MHz
The TPS55330 regulates the output voltage with
Synchronization Capability to External Clock
current mode PWM (pulse width modulation) control,
and has an internal oscillator. The switching
Adjustable Soft-Start Time
frequency of PWM is set by either an external resistor
Pulse-Skipping for Higher Efficiency at Light
or by synchronizing to an external clock signal. The
Loads
user can program the switching frequency from
Cycle-by-Cycle Current Limit, Thermal
100 kHz to 1.2 MHz.
Shutdown, and UVLO Protection
The device features a programmable soft-start
QFN-16 (3mmx3mm) with PowerPad™
function to limit inrush current during start-up and has
other built-in protection features including cycle-by-
Wide –40°C to 150°C Operating T
J
Range
cycle over current limit and thermal shutdown.
APPLICATIONS
The TPS55330 is available in a small 3mm x 3mm
16-pin QFN with PowerPad™ for enhanced thermal
3.3-V, 5-V, 12-V Power Conversion
performance.
Boost, SEPIC, and Flyback Topologies
Thunderbolt Port, Power Docking for Tablets
and Portable PCs
Industrial Power Systems
ADSL Modems
TYPICAL APPLICATION (BOOST)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPad is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PowerPAD
(17)
16
SS
EN
VIN
SW
FREQ
NC
PGND
PGND
SW
SW
NC
PGND
SYNC
AGND
COMP
FB
15 14 13
5
6 7 8
1
2
3
4
12
11
10
9
TPS55330
SLVSBX8 MAY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
T
J
PART NUMBER PACKAGE
-40°C to 150°C TPS55330RTE QFN-16
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
PIN ASSIGNMENTS
QFN-16 PACKAGE
(Top View)
PIN FUNCTIONS
PIN
DESCRIPTION
NO.
NAME
QFN-16
VIN 2 The input supply pin to the IC. Connect VIN to a supply voltage between 2.9V and 16V. It is acceptable for the voltage on the
pin to be different from the boost power stage input.
SW 1, 15, 16 SW is the drain of the internal power MOSFET. Connect SW to the switched side of the boost or SEPIC inductor or the flyback
transformer.
FB 8 Error amplifier input and feedback pin for positive voltage regulation. Connect to the center tap of a resistor divider to program
the output voltage.
EN 3 Enable pin. When the voltage of this pin falls below the enable threshold for more than 1ms, the IC turns off.
COMP 7 Output of the transconductance error amplifier. An external RC network connected to this pin compensates the regulator
feedback loop.
SS 4 Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start timing.
FREQ 9 Switching frequency program pin. An external resistor connected between the FREQ pin and AGND sets the switching
frequency.
AGND 6 Signal ground of the IC.
PGND 11, 12, 13 Power ground of the IC. It is connected to the source of the internal power MOSFET switch.
SYNC 5 Switching frequency synchronization pin. An external clock signal can be used to set the switching frequency between 200kHz
and 1.0MHz. If not used, this pin should be tied to AGND.
NC 10, 14 Reserved pin that must be connected to ground.
PowerPAD 17 The PowerPAD should be soldered to the AGND. If possible, use thermal vias to connect to internal ground plane for improved
power dissipation.
2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :TPS55330
SW
Ramp
Generator
Lossless
Current Sense
EN
PGND
Error
Amp
VIN
PWM
Control
COMP
SS
FREQ
SYNC
FB
AGND
1.229V
Reference
S
Oscillator
Gate
Driver
TPS55330
www.ti.com
SLVSBX8 MAY 2013
FUNCTIONAL BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
(1)
over operating temperature range (unless otherwise noted)
VALUE
UNIT
MIN MAX
Supply voltages on pin VIN
(2)
–0.3 18 V
Voltage on pin EN
(2)
–0.3 18 V
Voltage on pins FB, FREQ, and COMP
(2)
–0.3 3 V
Voltage on pin SS
(2)
–0.3 5 V
Voltage on pin SYNC
(2)
–0.3 7 V
Voltage on pin SW
(2)
–0.3 24 V
Operating junction temperature range –40 150 °C
Storage temperature range –65 150 °C
(HBM) QSS 009-105 (JESD22-A114A) 2 kV
Electrostatic discharge
(CDM) QSS 009-147 (JESD22-C101B 01) 500 V
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3
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TPS55330
SLVSBX8 MAY 2013
www.ti.com
THERMAL INFORMATION
TPS55330
THERMAL METRIC
(1)
QFN UNITS
16 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
43.3
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
38.7
θ
JB
Junction-to-board thermal resistance
(4)
14.5
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
0.4
ψ
JB
Junction-to-board characterization parameter
(6)
14.5
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
3.5
space
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
V
IN
Input voltage range 2.9 16 V
V
OUT
Output voltage range V
IN
22 V
V
EN
EN voltage range 0 16 V
V
SYN
External switching frequency logic input range 0 5 V
T
A
Operating free-air temperature –40 125 °C
T
J
Operating junction temperature –40 150 °C
ELECTRICAL CHARACTERISTICS
V
IN
= 5 V, T
J
= –40°C to +150°C, unless otherwise noted. Typical values are at T
A
= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
V
IN
Input voltage range 2.9 16 V
I
Q
Operating quiescent current into Vin Device non-switching, V
FB
= 2 V 0.5 mA
I
SD
Shutdown current EN = GND 2.7 10 µA
V
UVLO
Under-voltage lockout threshold V
IN
falling 2.5 2.7 V
V
hys
Under-voltage lockout hysteresis 120 140 160 mV
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