555 Bistable Timer

WiselabCMU
517
1
0
0
Test PCB for 555 Bistable mode
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CERN Open Hardware Licence 1.2 / CERN OHL 1.2

Published: January 18, 2016 In development

Project Description

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Project description
Playing around with Upverter's Interface by designing a 555 Bistable circuit
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Design Files

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Component (4)
Qty
Description
Capacitor

C1

1
Generic Capacitor (10nF)
PJ-037BH

J2

1
DC POWER JACK
3 Pin Header

J1

1
3 pin Header, 0.1" / 2.54mm Pitch, Through-hole, Generic
NE555P

U1

1
General purpose timer 1mHz to 100 kHz

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